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www.gennum.com gf9330 high performance hdtv/sdtv deinterlacer gf9330 data sheet 1 of 42 proprietary and confidential 18283 - 4 june 2004 features ? 10/8-bit progressive scan output up to 1080p60 ? support for multiplexed and non-mutiplexed y/c video ? multi-directional edge detection processing ? adaptive inter-field motion detection ? seamless interface to gennum's gf9331 motion co- processor ? fully configurable to support custom video modes ? 3:2 film mode operation for hdtv/sdtv inputs ? programmable noise reduction and detail enhancement ? de-interlace, pass-through and film rate down conversion modes of operation ? seamless interface to popular adcs and ntsc/pal decoders ? ability to extract hvf information from embedded trs ? selectable rounding and clipping of output data ? selectable blanking of active video lines ? hvf output signals with programmable output video cropping ? serial/parallel host interface ? 3.3v supply for device i/o and 2.5v for core logic ? 5v tolerant inputs applications ? hdtv up/down converters ? production equipment ? video walls ? projection systems ? plasma displays ?lcd tvs ? home theatre systems ? hd dvd players device overview the gf9330 is a 10-bit high performance vdsp engine that performs high quality motion adaptive de-interlacing of interlaced digital video signals. the gf9330 supports standard definition (sdtv) and high definition (hdtv) signal formats and clock rates up to 1080p60 with support for arbitrary display modes. the gf9330 uses multi-directio nal adaptive filters for edge processing, an adaptiv e vertical motion filter and an adaptive inter-field motion filter. the gf9330 features detail enhancement and noise reduction capabilities. the gf9330 also supports 3:2 pull-down, st atic/freeze-frame detection and compensation and film rate conversions. the gf9330 may operate as a stand-alone de-in terlacer or may be used with the gf9331 motion co-processor to enable higher quality hd/ sd de-interlacing with edge and vertical motion detection. the two devices can be configured in tandem such that the gf9331 sends edge detection and vertical motion filter control information to the gf9330. these control signals adaptively switch the gf9330's internal filters on a pixel-by-pixel basis. the gf9330 integrates all required line delays and seamlessly interfaces to off chip sdrams that form the required field delays. the device may also operate in by-pass mode should no processing of the input signal be desired. ordering information block diagram part number package temp. range GF9330-CBP 328 pin bga 0 o c to 70 o c noise reducer detail enhancer 3:2 pulldown detector inter-field motion detector edge adaptive interpolator vertical motion adaptive interpolator inter-field motion adaptive interpolator field merging selector output processing host interface timing generator external memory interface input processing control bus from gf9331 processed y/c y/c
gf9330 data sheet 2 of 42 proprietary and confidential 18283 - 4 june 2004 contents contents ...................................................................................................................... .2 1. pin descriptions ........................................................................................................3 2. electrical characteristics...........................................................................................8 2.1 5v tolerant inputs ...........................................................................................8 2.2 esd tolerance ................................................................................................8 2.3 3.3v supply for device i/0 and 2.5v fo r core logic .......................................8 3. detailed device description .. ..................................................................................12 3.1 supported input video formats .............. .............. .............. .............. ............12 3.2 input synchronization ...................................................................................14 3.3 seamless interface to the gf9331 motion co-processor for directional filter control .................................................................................................17 3.4 seamless interface to external sdrams .....................................................18 3.5 host interface ................................................................................................18 3.6 closed caption blanking ...............................................................................30 3.7 programmable noise reduction and deta il enhancement ...........................30 3.8 reset ..........................................................................................................31 3.9 modes of operation ....... .............. .............. .............. .............. .............. .........31 3.10 output data formats ..................................................................................33 3.11 sequence detection ........ .............. .............. .............. .............. ........... .........37 4. package dimensions ..............................................................................................41 revision history .........................................................................................................42
gf9330 data sheet 3 of 42 proprietary and confidential 18283 - 4 june 2004 1. pin descriptions figure 1-1: top view pin out 328 bga a b c d j k e f g h l m n p w y r t u v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 reset y_in9 s2_dat0 s2_dat1 y_in8 y_in5 y_in7 y_in4 s2_dat2 s2_dat3 s2_dat4 s2_dat5 y_in6 y_in3 s2_dat6 s2_dat7 s2_dat8 s2_dat9 s2_dat12 s2_dat13 s2_dat10 s2_dat11 s2_dat14 s2_dat15 s2_dat16 s2_dat17 s2_dat20 s2_dat21 s2_dat18 s2_dat19 s2_dat22 s2_dat23 s2_dat25 s2_dat26 s2_dat29 s2_dat30 s2_dat27 s2_dat28 s2_dat31 s2_dat32 s2_dat36 s2_dat35 s2_clk s2_dat39 s2_dat34 s2_dat33 s2_dat38 s2_dat37 s2_dat44 s2_dat43 s2_addr0 s2_dat47 s2_dat42 s2_dat41 s2_dat46 s2_dat45 s2_addr4 s2_addr3 s2_addr8 s2_addr7 s2_addr2 s2_addr1 s2_addr6 s2_addr5 s2_addr12 s2_addr11 s2_cs s2_cas s2_addr10 s2_addr9 s2_addr13 y1_out11 s2_we s2_ras vclk_out lock_32 xseq1 xseq3 xseq0 xseq2 y_in2 vclk_in y_in1 mode2 ser_md memclk_in std4 std1 y_in0 mode1 host_en mode0 std3 std0 std2 xvoclk_sl gnd vdd_clkd vdd_int vdd_int vss_clkd gnd vdd_int gnd vdd_io vdd_io s2_dat24 gnd vdd_io gnd vdd_int s2_dat40 gnd gnd vdd_io vdd_io gnd vdd_int gnd vdd_int gnd nc y1_out4 y1_out5 y1_out0 y2_out8 y1_out1 y2_out9 y1_out9 y1_out6 y1_out10 y1_out7 y1_out2 y2_out10 y1_out3 y2_out11 xvoclk_in c_in7 lock_22 c_in6 c_in0 fil_sel0 c_in1 fil_sel1 c_in9 c_in5 c_in8 c_in4 c_in2 fil_sel2 c_in3 fil_sel3 vdd_io gnd vdd_int gnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd tgnd vdd_io gnd gnd vdd_io y2_out4 nc y2_out5 y2_out1 nc c1_out9 y2_out0 c1_out8 y2_out6 y2_out2 y2_out7 y2_out3 c1_out11 c1_out7 c1_out10 c1_out6 fvh_en a_d f_in cs dat_io4 dat_io0 dat_io5 dat_io1 v_in r_w h_in ff_en dat_io6 dat_io2 dat_io7 dat_io3 vdd_io gnd gnd nc gnd vdd_int vdd_int vdd_io vdd_io s1_dat41 gnd vdd_io gnd vdd_int s1_dat25 gnd gnd gnd vdd_int vdd_io vdd_io vdd_int gnd c1_out5 c1_out1 c1_out4 c1_out0 c2_out9 nc c2_out8 c2_out5 c1_out3 c2_out11 c1_out2 c2_out10 c2_out7 c2_out4 c2_out6 c2_out3 tdi tclk tms gnd gnd s1_ras s1_we s1_addr13 gnd gnd gnd s1_addr10 s1_cas s1_cs s1_addr11 s1_addr12 s1_addr6 s1_addr7 s1_addr2 s1_addr3 s1_addr8 s1_addr9 s1_addr4 s1_addr5 s1_dat46 s1_dat47 s1_dat42 s1_dat43 s1_addr0 s1_addr1 s1_dat44 s1_dat45 s1_dat37 s1_dat38 s1_dat34 s1_dat35 s1_dat39 s1_dat40 s1_dat36 s1_clk s1_dat33 s1_dat32 s1_dat29 s1_dat28 s1_dat31 s1_dat30 s1_dat27 s1_dat26 s1_dat24 s1_dat23 s1_dat20 s1_dat19 s1_dat22 s1_dat21 s1_dat18 s1_dat17 s1_dat16 s1_dat15 s1_dat12 s1_dat11 s1_dat14 s1_dat13 s1_dat10 s1_dat9 s1_dat8 s1_dat7 c2_out2 s1_dat4 s1_dat6 s1_dat5 s1_dat3 s1_dat2 c2_out1 f_out c2_out0 h_out s1_dat1 s1_dat0 v_out tdo y1_out8 top view gf9330 pin out 328 bga vdd_io: +3.3v vdd_int: +2.5v gnd/tgnd: 0v nc: no connection
gf9330 data sheet 4 of 42 proprietary and confidential 18283 - 4 june 2004 table 1-1: pin descriptions symbol pin grid type description reset a1 i active low, asynchronous reset . resets all internal logic to default conditions. should be applied on power up. vclk_in f1 i video input clock. when the input is sdtv the input clock will be 27, 36, 54 or 72mhz. when the input format is hdtv, t he input clock will be 74.25 or 74.25/ 1.001mhz. memclk_in h1 i memory clock for sdram oper ation to support hd modes, 90mhz input (supplied by an off-chip crystal oscillator). xvoclk_in j1 i external video output clock. this input may be used instead of the internal vclk_in clock doubler to supply the video output clock vclk_out. xvoclk_sl h4 i control signal input. when high, selects xvoclk_in; when low, selects the internal vclk_in clock doubler for generation of the video output vclk_out signal. y_in[9:0] b1, c1, c2, c3, d1, d2, d3, e1, e2, e3 i 10/8-bit input bus for separate luminanc e or multiplexed luminance and colour difference video data. when supplying 8-bit data to the gf9330, y_in[1:0] will be set low and the 8-bit data supplied to y_in[9:2]. c_in[9:0] j3, j4, k1, k2, k3, k4, l4, l3, l2, l1 i 10/8-bit input bus for colour differ ence for video data. when supplying 8-bit data to the gf9330, c_in[1:0] will be set low and the 8-bit data supplied to c_in[9:2]. fil_sel[3:0] m4, m3, m2, m1 i filter selection control bus. fil_sel[3:0] are used to switch the gf9330?s internal directional filters on a pixel by pixel basis. fil_sel[3:0] is supplied by the gf9331. f_in n2 i video timing control. f_in identifies the odd and even fields in the incoming video signal. f_in will be low in field 1 and high in field 2. v_in n3 i video timing control. v_in represent s the vertical blanking signal associated with the incoming video signal. v_in is high during the vertical blanking interval and low during active video. h_in n4 i video timing control. h_in repr esents the horizontal blanking signal associated with the incoming video signa l. h_in is high during horizontal blanking and low during active video. fvh_en n1 i control signal input. when high, the f_in, v_in, and h_in input pins will be used for video data signalling. when low, embedded trs?s will be detected for video data timing. ff_en p4 i control signal input. when high, ff_en enables the gf9330?s internal freeze frame compensation. see 3.11.4 static and freeze frame detection/ compensation . lock_22 j2 i control signal input. for 2:2 pull- down compensation, the lock_22 pin will be used to identify the presence of a 2:2 sequence in the input video stream. std[4:0] g2, g3, g4, h2, h3 i video format definition. defines the video standard when operating without the host interface. see table 3-1: encoding of std[4:0] for selecting input data format . mode[2:0] f2, f3, f4 i operating mode selection. defines the mode of operation when operating without the host interface. see 3.9 modes of operation .
gf9330 data sheet 5 of 42 proprietary and confidential 18283 - 4 june 2004 host_en e4 i host interface enable. when set high, the gf9330 will be configured through the host interface. on a high to low transition of host_en the gf9330 will replace all register settings in the host interface with the values present on the external pins of the dev ice including: std[4:0], mode[2:0], fvh_en, ff_en and xvoclk_sl. ser_md g1 i host interface mode selection. enables serial mode operation when high. enables parallel mode operation when low. cs p2 i functions as an active low chip sele ct input for host interface parallel mode operation. functions as a serial clock input for hos t interface serial mode operation. dat_io[7:0] r4, r3, r2, r1, t4, t3, t2, t1 i/o host interface bi-directional data bus for parallel mode. in serial mode, dat[7] serves as the serial data output pin and da t[0] serves as the serial data input pin. r_w p3 i host interface read/write control for parallel mode. a read cycle is defined when high, a write cycle is defined when low. a_d p1 i host interface address/data control for parallel mode. the data bus contains an address when high, a data word when low. in serial mode, this pin serves as the chip select (active low). vclk_out a20 o video output clock. output frequency based on selected output standard. see 3.9 modes of operation . y1_out[11:0] d18, e20, e19, e18, f20, f19, f18, f17, g20, g19, g18, g17 o output data bus for separate luminance or multiplexed luminance and colour difference video data. see 3.10.2 12-bits output resolution . y2_out[11:0] h20, h19, h18, h17, j20, j19, j18, j17, k20, k19, k18, l18 o output data bus for luminance video data during dual pixel mode operation. see 3.10.2 12-bits output resolution . c1_out[11:0] l19, l20, m17, m18, m19, m20, n17, n18, n19, n20, p17, p18 o output data bus for colour difference video data. see 3.10.2 12-bits output resolution . c2_out[11:0] p19, p20, r17, r18, r19, r20, t18, t19, t20, u18, u19, u20 o output data bus for colour differ ence video data during dual pixel mode operation. see 3.10.2 12-bits output resolution . lock_32 b20 o control signal output. when the gf 9330?s internal algorithm detects a 3:2 sequence in the video stream the lock_32 signal is set high. otherwise, lock_32 is low. xseq[3:0] d19, d20, c19, c20 i/o control signal input/output. for external 3:2 sequence detection, the xseq[3:0] pins will be used to provide the 3:2 sequence information. for internal 3:2 detection the xseq[3:0] pi ns output the detected 3:2 sequence information. see figure 3-12: sequence detection input signals . h_out v20 o output control signal. h_out is high during horizontal blanking. f_out v19 o output control signal. f_out is low during field 1 and high during field 2. v_out w20 o output control signal. v_out is high during vertical blanking. s1_clk y10 o sdram bank 1 clock. s1_cs y3 o active low sdram chip select for field buffer 1. table 1-1: pin descriptions (continued) symbol pin grid type description
gf9330 data sheet 6 of 42 proprietary and confidential 18283 - 4 june 2004 s1_ras w2 o active low sdram row address strobe for field buffer 1. s1_cas w3 o active low sdram column address strobe for field buffer 1. s1_we y2 o active low sdram write enable for field buffer 1. s1_addr[13:0] v3, y4, w4, v4, y5, w5, v5, u5, y6, w6, v6, u6, y7, w7 o sdram address for field buffer 1. s1_dat[47:0] v7, u7, y8, w8, v8, u8, t8, y9, w9, v9, u9, w10, v10, u10, u11, v11, w11, y11, u12, v12, w12, y12, t13, u13, v13, w13, y13, u14, v14, w14, y14, u15, v15, w15, y15, u16, v16, w16, y16, u17, v17, w17, y17, v18, w18, y18, w19, y19 i/o sdram data for field buffer 1. s2_clk a12 o sdram bank 2 clock. s2_cs a18 o active low sdram chip select for field buffer 2. s2_ras b19 o active low sdram row address strobe for field buffer 2. s2_cas b18 o active low sdram column address strobe for field buffer 2. s2_we a19 o active low sdram write enable for field buffer 2. s2_addr[13:0] c18, a17, b17, c17, d17, a16, b16, c16, d16, a15, b15, c15, d15, a14 o sdram address for field buffer 2. s2_dat[47:0] b14, c14, d14, a13, b13, c13, d13, e13, b12, c12, d12, a11, b11, c11, d11, d10, c10, b10, a10, d9, c9, b9, a9, e8, d8, c8, b8, a8, d7, c7, b7, a7, d6, c6, b6, a6, d5, c5, b5, a5, d4, c4, b4, a4, b3, a3, b2, a2 i/o sdram data for field buffer 2. tdi u1 i jtag data input; connect to gnd if not used. tms v2 i jtag mode select; connect to gnd if not used. tclk v1 i jtag test clock; connect to gnd if not used. tdo y20 o jtag data output. vdd_clkd f5 na 2.5v supply for the internal clock doubler. vss_clkd g5 na ground connection for the internal clock doubler. vdd_io e7, e10, e15, f7, f15, j5, j16, m16, n5, r7, r15, t7, t10, t15 na 3.3v supply. table 1-1: pin descriptions (continued) symbol pin grid type description
gf9330 data sheet 7 of 42 proprietary and confidential 18283 - 4 june 2004 vdd_int e6, e12, f6, f16, g6, g16, l5, p16, r6, r16, t6, t12 na 2.5v supply. gnd / tgnd e5, e9, e11, e14, e16, f14, g15, h5, h6, h16, k5, k16, l16, m5, n16, p5, p6, p15, t5, t9, t11, t14, t16, j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12, u2, u3, u4, w1, y1 na device ground / thermal gro und (electrically equivalent). nc e17, k17, l17, r5, t17 no connection. table 1-1: pin descriptions (continued) symbol pin grid type description
gf9330 data sheet 8 of 42 proprietary and confidential 18283 - 4 june 2004 2. electrical characteristics 2.1 5v tolerant inputs input cells used in the design are able to withstand 3.3v or 5v cmos input signals without degrading performance or long-term reliability as well as ttl compatible inputs. 2.2 esd tolerance gf9330 has 2kv esd protection. esd te sting is done in accordance with gennum?s standard esd testing procedure. 2.3 3.3v supply for device i/0 and 2.5v for core logic the gf9330 operates from a single +3.3v su pply for device i/o, and a single +2.5v supply for core logic. table 2-1: absolute maximum ratings parameter symbol value device i/o supply voltage v ddio -0.5 to tbd v device core supply voltage v ddcore -0.5 to tbd v input voltage range (any input) v in -0.5 < v in < +4.6v operating temperature range t a 0 o c < t a < 70 o c storage temperature range t s -40 o c < t s < 125 o c lead temperature (soldering 10 seconds) 260 o c table 2-2: dc electrical characteristics v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes device i/o supply voltage v ddio +3.0 +3.3 +3.6 v a device core supply voltage v ddcore +2.25 +2.5 +2.75 v a device i/o supply current v ddio =3.3v i ddio -43-ma a device core supply current v ddcore =2.5v i ddcore - 456 - ma a input leakage current i in =0v or i in =v dd i leak --10 a a
gf9330 data sheet 9 of 42 proprietary and confidential 18283 - 4 june 2004 tristate leakage current i trileak --10 a a input logic low voltage v il -- 0.8v a input logic high voltage v ih 2.1 - - v a output logic low voltage i ol = 4ma v ol -0.20.4v a output logic high voltage i oh = -4ma v oh 2.7 - - v a a. production, test and qa are performed at room temperature. table 2-2: dc electrical char acteristics (continued) v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes table 2-3: ac electrical characteristics - video interfaces the video interface signals include: vclk, y_in[9:0} , c_in[9:0}, fil_sel[3:0], f_ in, v_in, h_in, fvh_en, ff_en, lock_22, y1_out[11:0], y2_out[11:0], c1_out[11:0], c2_out[11:0], lock_32, xseq[3:0], h_out, f_out and v_out. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes clock input frequency f hsci - 74.25 83 mhz a , b input data setup time t su 2.5 - - ns a , c input data hold time t ih 1.5 - - ns a , c input clock duty cycle 40 - 60 % a output data delay time v ddio =3.6v, c l =15pf load t od - - 10.0 ns a output data hold time v ddio =3.6v, c l =15pf load t oh 2.0 - - ns a output enable time v ddio =3.6v, c l =15pf load t oen - - 10 ns a output disable time v ddio =3.6v, c l =15pf load t odis - - 10 ns a output data rise/fall time v ddio =3.6v, c l =15pf load t odrf --2.0ns a , d a.based on simulation results, verified during device characterization process. b.also supports 74.25/1.001mhz. c.50% levels. d.20% to 80% levels.
gf9330 data sheet 10 of 42 proprietary and confidential 18283 - 4 june 2004 table 2-4: ac electrical characteristics - sdram interfaces the sdram 1 interface sign als include s1_clk, s1_cs , s1_ras , s1_cas , s1_we , s1_addr[13:0] and s1_dat[47:0]. the sdram 2 interface sign als include s2_clk, s2_cs , s2_ras , s2_cas , s2_we , s2_addr[13:0] and s2_dat[47:0]. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes clock input frequency f hsci_sd -8590mhz a input data setup time t su_sd 2.0 - - ns a , b input data hold time t ih_sd 2.5 - - ns a , b input clock duty cycle 40 - 60 % a output data delay time v ddio =3.6v, c l =15pf load t od_sd --9.1ns a output data hold time v ddio =3.6v, c l =15pf load t oh_sd 2.0 - - ns a output enable time v ddio =3.6v, c l =15pf load t oen_sd - - 20 ns a , c output disable time v ddio =3.6v, c l =15pf load t odis_sd - - 20 ns a , c output data rise/fall time v ddio =3.6v, c l =15pf load t odrf_sd --2.0ns a , d a.based on simulation results, verified during device characterization process. b.50% levels. c.two clock cycles allocated for data bus turnaround. d.20% to 80% levels. table 2-5: ac electrical characteristics - host interfaces the host interface signals include host_en, ser_md, cs , dat_io[7:0], r_w and a_d. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes clock input frequency f hsci_hi --20mhz a input data setup time t su_hi 5- -ns a , b input data hold time t ih_hi 1.5 - - ns a , b input clock duty cycle 40 - 60 % a output data delay time v ddio =3.6v, c l =15pf load t od_hi - - 10.0 ns a
gf9330 data sheet 11 of 42 proprietary and confidential 18283 - 4 june 2004 output data hold time v ddio =3.6v, c l =15pf load t oh_hi 2.0 - - ns a output enable time v ddio =3.6v, c l =15pf load t oen_hi - - 15 ns a output disable time v ddio =3.6v, c l =15pf load t odis_hi - - 15 ns a output data rise/fall time v ddio =3.6v, c l =15pf load t odrf_hi --2.0ns a , c a.based on simulation results, verified during device characterization process. b.50% levels. c.20% to 80% levels. table 2-5: ac electrical characteristic s - host interfaces (continued) the host interface signals include host_en, ser_md, cs , dat_io[7:0], r_w and a_d. v ddio = 3.0 to 3.6v, v ddcore = 2.25 to 2.75v, t a = 0 to 70 o c, unless otherwise shown. parameter conditions symbol min typ max units notes
gf9330 data sheet 12 of 42 proprietary and confidential 18283 - 4 june 2004 3. detailed device description 3.1 supported input video formats the gf9330 supports multiple input data formats with multiplexed or separate y/ c channels. data is supplied to the gf9330 through the y_in[9:0] and the c_in[9:0] busses. table 3-1: encoding of std[4:0] for selecting input data format outlines the data formats that are supporte d according to the setting of the control register bits std[4:0] note: for all progressive video standards the gf9330 must be manually set to bypass mode (mode[2:0] = 111). see 3.5 host interface for details. table 3-1: encoding of std[4:0] for selecting input data format std std[4:0] description 0 00000 525i (30/1.001) component smpte 125m. multiplexed ycbcr data applied to y_in. c_in is set low. note: input clock is 27mhz. 1 00001 reserved 2 00010 525i (30/1.001) component 16x9 smpte 267m. multiplexed ycbcr data applied to y_in. c_in is set low. note: input clock is 36mhz. 3 00011 reserved 4 00100 625i (25hz) component ebu tech. 3267e. multiplexed ycbcr data applied to y_in. c_in is set low. note: input clock is 27mhz. 5 00101 reserved 6 00110 625i (25hz) component 16x9 itu-r bt.601-5 part b. multiplexed ycbcr data applied to y_in. c_in is set low. note: input clock is 36mhz. 7 00111 reserved 8 01000 525p (60/1.001hz) smpte 293m. ycbcr data stream applied to y_in. c_in is set low. note: input clock is 54mhz. 9 01001 reserved 10 01010 reserved 11 01011 reserved 12 01100 625p (50hz) itu-r bt.1358. ycbcr data stream applied to y_in. c_in is set low. note: input clock is 54mhz. 13 01101 625p (50hz) 16 x 9 with 18mhz sampling. ycbcr data stream applied to y_in. c_in is set low. note: input clock is 72mhz. 14 01110 generic sd input data format with 4:1:1 sampling. ycbcr data is applied to both y_in and c_in. externally supplied f_in, v_in and h_in signals are us ed to synchronize the input data stream. note: input clock is 27mhz.
gf9330 data sheet 13 of 42 proprietary and confidential 18283 - 4 june 2004 15 01111 generic sd input data format with 4:2:2 sampling and single multiplexed ycbcr input format. ycbcr data applied to y_in. c_in is set low. externally supplie d f_in, v_in and h_in signals are used to synchronize the input data stream. note: input clock is 27 or 36mhz. 16 10000 720p (60 & 60/1.001hz) smpte 296m-2001. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25 mhz or 74.25/1.001mhz. 17 10001 720p (30 & 30/1.001hz) smpte 296m-2001. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.2 or 74.2/1.001mhz. 18 10010 1080p (30 & 30/1.001hz) smpte 274m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. 19 10011 720p (50hz) smpte 296m-2001. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 20 10100 1080p (25hz) smpte 274m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 21 10101 720p (25hz) smpte 296m-2001. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 22 10110 1080p (24 & 24/1.001hz) smpte 274m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. 23 10111 720p (24 & 24/1.001hz) smpte 296m-2001. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. 24 11000 1080i (30 & 30/1.001hz) smpte 274m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. 25 11001 1080p (30 & 30/1.001hz in segmented frame format) smpte rp211-2000. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. 26 11010 1080i (25hz) smpte 274. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 27 11011 1080p (25 hz in segmented frame format) smpte rp211-2000. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 28 11100 1080i (25hz) smpte 295m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 29 11101 1080p (24 & 24/1.001hz in segmented frame format) smpte rp211-2000. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74. 25mhz or 74.25/1.001mhz. table 3-1: encoding of std[4:0] for select ing input data format (continued) std std[4:0] description
gf9330 data sheet 14 of 42 proprietary and confidential 18283 - 4 june 2004 3.2 input synchronization the gf9330 obtains relevant timing information from either embedded trs information or externally supplied h_in, v_in and f_in signals. when fvh_en is set high, using either the host interface or the external pin, the gf9330 relies on the externally supplied h_in, v_in and f_in signals for timing information. when fvh_en is set low, the gf9330 will extr act the embedded trs timing information from the video da ta stream and will ignore any timing information present on the f_in, v_in and h_in pins. 3.2.1 support for both 8- bit and 10-bit input data the gf9330 supports 8 and 10-bit input data. when operating with 8-bit input data, the two lsbs of the gf9330?s 10-bit input should be set low and the input data is applied to the 8 msbs of the input bus. 3.2.2 generic input format signalling the gf9330 supports generic input data form ats with either 4:1:1 or 4:2:2 sampling structures handling up to 2046 active sa mples per line with a total maximum line width of 4096 (active + blanking) samples. in addition, there is a limit of 2048 lines per interlaced frame. the following host interface parameters are used to describe the generic input data form at relative to the f_in, v_in and h_in signals. see figure 3-1: generic input format definition . 30 11110 1035i (30hz) smpte 260m. y data applied to y_in. cb cr data applied to c_in. note: input clock is 74.25mhz. 31 11111 generic hd input data format with 4:2:2 sampling and a separate y/c format. y data applied to y_in. cb cr data applied to c_in. externally supplied f_in, v_in and h_in signals are used to synchronize the input data stream. note: input clock is 74. 25mhz or 74.25/1.001mhz. table 3-1: encoding of std[4:0] for select ing input data format (continued) std std[4:0] description
gf9330 data sheet 15 of 42 proprietary and confidential 18283 - 4 june 2004 figure 3-1: generic input format definition 3.2.2.1 output h_blank_size this parameter defines the number of samples that comprise the horizontal blanking region. this parameter has a maximum value of 4095 and is to be less than the total line width (active + blanking) sample size. twelve bits within the host interface are dedicated to this parameter. the gf9330 only stores and processes active video samples only (i.e. h_in=0). 3.2.2.2 v_blank_size_odd this parameter defines the number of lines that comprise the vertical blanking interval that follows the odd field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. the gf9330 only stores and processes active video samples (i.e. v_in=0). see figure 3-1: generic input format definition . 3.2.2.3 v_blank_size_even this parameter defines the number of lines that comprise the vertical blanking interval that follows the even field. this parameter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. the gf9330 only stores and processes active video samples (i.e. v_in=0). see figure 3-1: generic input format definition . output h_blank_size v_blank_size_even v_blank_size_odd even field odd field odd field even field even field odd field v_offset_even f_offset_even v_offset_odd f_offset_odd v f 01 01 odd field even field
gf9330 data sheet 16 of 42 proprietary and confidential 18283 - 4 june 2004 3.2.2.4 v_offset_odd this defines the number of lines from the v_in pin eav transition to the end of the odd active video field region. this param eter has a maximum value of 255. eight bits within the host interface are dedicated to this parameter. this parameter has been added to accommodate all video deco ders which that output non-standard timing for the v_in signal. see figure 3-2: vertical offset definition . figure 3-2: vertical offset definition 3.2.2.5 v_offset_even this parameter defines the number of lines from the v_in pin eav transition to the end of the even active vide o field region. this parameter has a maximum value of 255. eight bits within the host interfac e are dedicated to this parameter. this parameter has been added to accommodate all video decoders that output non- standard timing for the v_in signal. see figure 3-2: vertical offset definition . 3.2.2.6 f_offset_odd this defines the number of lines from the f_in pin eav transition to the vertical blanking interval following the odd field. this parameter has a maximum value of 255. eight bits within the host interfac e are dedicated to this parameter. this parameter has been added to accommodate all video decoders that output non- standard timing for the f_in signal. see figure 3-1: generic input format definition . 3.2.2.7 f_offset_even this register defines the nu mber of lines from the f_ in pin eav transition to the vertical blanking interval following the even field. this parameter has a maximum value of 255. eight bits within the host in terface are dedicated to this parameter. this parameter has been added to accommodate all video decoders which output non-standard timing for the f_in signal. see figure 3-1: generic input format definition . 3.2.2.8 h_polarity this register defines the polarity of th e h_in pin. with h_polarity set low, a falling transition on the h_in pin indicate s end of active video. with h_polarity set high, a rising transition on the h_in pin indicates the end of active video. one bit within the host interface is dedicated to this parameter. h_in vertical blanking region v_in v_offset_odd/even last active line
gf9330 data sheet 17 of 42 proprietary and confidential 18283 - 4 june 2004 3.2.2.9 f_polarity this register defines the polarity of the f_in pin. refer to table 3-2: f_polarity for f_polarity encoding. one bit within the host interface is dedicated to this parameter. 3.2.2.10 v_polarity this register defines the polarity of the v_in pin. with v_polarity set low, a falling transition on the v_in pin indicates the end of active video. with v_polarity set high, a rising transition on the v_in pin indicates the end of active video. one bit within the host in terface is dedicated to this parameter. 3.3 seamless interface to the gf9331 motion co-processor for directional filter control the gf9330 can operate as a stand-alone motion adaptive de-interlacer or can operate in conjunction with the gf9331 motion co-processor. the gf9331 contains adaptive multi-directional edge detection and vertical motion detection. control signals are fed back directly to the gf9330. these control signals adaptively switch the gf9330?s internal edge & vertical motion de-interlacing filters on a pixel by pixel basis. these control signals are fed to the gf9330 by the gf9331 over the fil_sel[3:0] control bus. when the gf9330 is not being used with the gf9331, the fil_sel[3:0] inputs should be set low. note : when using the gf9331, the y_in[9:0 ] of the gf9330 must be connected to y_out[9:0] of the gf9331 and c_in[9:0 ] of the gf9330 must be connected to the c_out[9:0] of the gf9331. fil_sel[3:0] of the gf9330 must also be connected to fil_sel[3:0] of the gf93 31. the timing information from the gf9331 is provided exclusively through the f_out, h_out and v_out pins which must be connected to the f_in, h_in and v_in pins of the gf9330. table 3-2: f_polarity f_polarity register f_in pin f_in pin function 0 0 even field 0 1 odd field 1 0 odd field 1 1 even field
gf9330 data sheet 18 of 42 proprietary and confidential 18283 - 4 june 2004 3.4 seamless interface to external sdrams for all sd video formats, the gf9330 requires two 1m x 24-bit (min.) sdram field buffers. to pass hd video formats in bypass mode , the gf9330 requires two field buffers, each implemented with a 1m x 48-bit (min. ) sdram configuration. to deinterlace hd formats, the memory requ irements increase to a 4m x 48-bit (min) sdram configuration. 3.5 host interface the gf9330 provides both a serial and parallel host interface control port for the configuration of internal parameters. the gf9330 is also able to operate in stand- alone mode, with no host interface control. in stand-alone mode, the video standard (std[4:0]) and mode of operati on (mode[2:0]) are set using dedicated pins on the device. these values are loaded into the device on a falling transition of host_en or after setting reset low. both the serial and parallel interfaces share common pins as described in table 3- 4: host interface common pins . table 3-3: sdram configuration format bypass configuration per bank a total of addr and bank b sdram properties (per bank) recomended min. freq. (mhz) min. access time (ns) cas latency sd yes 1(1mx24) 12 90 5.5 3 micron: mt48lc4m16a2, mt48lc8m16a2 no 1(1mx24 12 90 5.5 3 hd yes 1(1mx48) 12 90 5.5 3 no 1(1mx48) 14 90 5.5 3 a.there are 2. b.this is assuming a 8-column structure. table 3-4: host interface common pins gf9330 pin name parallel mode serial mode cs chip select sclk - serial clock dat_io[0] data/address (bit 0) sdi - serial data in dat_io[1] data/address (bit 1) (not used) dat_io[2] data/address (bit 2) (not used) dat_io[3] data/address (bit 3) (not used) dat_io[4] data/address (bit 4) (not used)
gf9330 data sheet 19 of 42 proprietary and confidential 18283 - 4 june 2004 3.5.1 host interface serial mode the gennum serial peripheral interface (gspi) is a 4 wire interface comprised of serial data in (sdi), serial data out (sdo), an active low serial chip select (scs ) and a clock (sclk). the interface operates in a master/slave co nfiguration, where the master provides the sclk, sdi, and scs signals to the slave or slaves. the master uc_sdo drives the sl ave(s) sdi input. the sdo pin is a tristate output that allows multiple devices to drive the master uc_sdi. serial mode operation supports both a continuous clock and a burst clock configuration. the serial mode interface is illustrated in the figure 3-3: host interface serial mode . figure 3-3: host interface serial mode 3.5.1.1 serial command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-configure control bit, nine reserved bits and a 5-bit address. as shown in figure 3-4: serial command word bit representation . figure 3-4: serial command word bit representation the r/w bit indicates a read command if r/w = high, and a write command when r/w = low. dat_io[5] data/address (bit 5) (not used) dat_io[6] data/address (bit 6) (not used) dat_io[7] data/address (bit 7) sdo - serial data out a_d address/data select scs - serial chip select r_w read/write select (not used) host_en host interface enable host interface enable ser_md low = parallel mode enable high = serial mode enable table 3-4: host interface common pins (continued) gf9330 pin name parallel mode serial mode uc_scs uc_sclk uc_sdo uc_sdi master (uc) scs (a_d) sclk (cs) sdi dat_io[0] sdo dat_io[7] slave (gf9330) (*) asic pin name r/w ac rsv rsv a0 a1 a2 a3 a4 rsv rsv rsv rsv rsv rsv rsv msb lsb
gf9330 data sheet 20 of 42 proprietary and confidential 18283 - 4 june 2004 3.5.1.2 auto-configure the auto-configure feature will be executed when the auto-configure control bit is set. all auto-configure registers will be upda ted to their approp riate settings based on the current video standard and operational mode. when setting the auto-configure bit, the command word should be set with only the ac bit set to 1. all of the 15 remainin g bits should be set to 0. to complete the auto-configuration 16 additional bits must be loaded into the device. the state of these bits can be either high or low. before auto-configuring the device, the standard and mode must be set using either the host interface (host_en = 1) or the external pins (with a fa lling transition of host_en). this simplifies configuration while allo wing customization of many features and format parameters. 3.5.1.3 serial data word description the serial data word consists of a 16-bit word as shown in figure 3-5: serial data word bit representation . serial data is transmit ted or received msb first. figure 3-5: serial data word bit representation both command and data words are clocked into the gf9330 on the rising edge of the serial clock (sclk), which may operate in either a continuous or burst fashion. the first bit (msb) of the se rial output (sdo) is available following the last falling sclk edge of the "read" command word. the remaining bits are clocked out on the falling edges of sclk. 3.5.1.4 serial write operation all write cycles consist of a command word followed by a data word, both transmitted to the gf9330 via sdi. the first 16-bit word transmitted following a falling transition of scs is a command word. several write cycles may be performed while scs is low. see figure 3-6: write cycle . figure 3-6: write cycle d15 d14 d13 d12 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d10 msb lsb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sclk scs r/w 0 au r a0 a1 a2 a3 a4 r r r r r rrr sdi 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d15 d14 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d12 d11 d10 sdo t su_hi t ih_hi t su_hi
gf9330 data sheet 21 of 42 proprietary and confidential 18283 - 4 june 2004 3.5.1.5 serial read operation all read cycles consist of a command word transmitted to the gf9330 via sdi followed by a data word transmitted from the gf9330 via sdo. the first 16-bit word transmitted following a fa lling transition of scs is a command word. several read cycles may be performed while scs is low. see figure 3-7: read cycle . figure 3-7: read cycle 3.5.2 host interface parallel mode the gennum parallel peripheral interface (g ppi) consists of an 8-bit multiplexed address/data bus (dat_io[7:0]), a chip select pin (cs ), a read/write pin (r_w), and an address/data pin (a_d) as shown in figure 3-8: parallel peripheral interface . figure 3-8: parallel peripheral interface data is strobed in/out of the parallel interface on the falling edge of cs . the gf9330 drives the dat_io[7:0] bus wh en the r_w pin is high and the cs pin is low, otherwise this port is in a high impedance state. 01234567891011121314 15 sclk scs r/w 1 au 0 r a0 a1 a2 a3 a4 r r r r r rrr sdi 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 sdo d15 d14 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d12 d11 d10 t oen_hi t od_hi t odis_hi a_d cs dat_io[7:0] r_w slave (gf9330) (*) asic pin name uc_a/d uc_cs uc_addr/dat uc_r/w master (uc)
gf9330 data sheet 22 of 42 proprietary and confidential 18283 - 4 june 2004 3.5.2.1 parallel address word description the 8-bit address word loads in the address to be accessed and allows the auto- configure bit to be set. the msb is th e auto-configure bit, followed by two reserved bits and a 5-bit address as shown in figure 3-9: parallel address word bit representation . figure 3-9: parallel addres s word bit representation 3.5.2.2 parallel write operation a write cycle to the parallel interface is shown in figure 3-10: write cycle to the parallel interface . first an 8-bit address word is provided to the dat_io bus by asserting the r_w pin to low and the a_d pin to high. the msb of the address word contains an auto-update flag, whic h allows automatic configuration of predefined registers. the 5 lsb's of the address word contain the address location for the read or write operation. the remaining address bits dat_io[6:5] are reserved. the address word is registered on the falling edge of cs . following this, the a_d pin is driven low and two data word s are sent upper byte (ub) word first and are each clocked in on the falling edge of cs . two 8-bit data words must follow each address word to occupy each 16-bit parameter, which are defined in figure 3-11: host interface register allocation . figure 3-10: write cycle to the parallel interface 3.5.2.3 parallel read operation a read cycle begins with an address write by asserting the r_w pin low and the a_d pin high. the address is cl ocked on the falling edge of cs . following the address, the r_w pin must be driven hi gh and a_d pin driven low to allow the upper byte of data to be clocked out on the first falling edge of cs followed by the lower byte on the seco nd falling edge of cs . ac rsv rsv a4 a0 a1 a3 a2 msb lsb address (ub) data_in (lb) data_in address (ub) data_out (lb) data_out dat_io[7:0] r_w a_d cs t odis_hi t oen_hi t su_hi t ih_hi
23 of 42 gf9330 data sheet proprietary and confidential 18283 - 4 june 2004 figure 3-11: host interf ace register allocation hex bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address 31 1f cmd_reset start_operation address 30 1e clk_x1_sel voclk_x1_sel ext_memclk_sel address 29 1d address 28 1c address 27 1b address 26 1a address 25 19 address 24 18 address 23 17 frame_regen address 22 16 odd_field_one_more e ven_field_one_more field2_has_top_line h_blank_size_1half address 21 15 progressive_input format_sd address 20 14 address 19 13 address 18 12 address 17 11 address 16 10 address 15 f address 14 e address 13 d address 12 c address 11 b address 10 a address 9 9 address 8 8 address 7 7 address 6 6 address 5 5 address 4 4 address 3 3 address 2 2 address 1 1 h_polarity v_polarity f_polarity fvh_en_bit crop_en cc_blank_en mode_32 ff_en_bit address 0 0 lock_32 ff_detect freeze_frame_threshold v_blank_offset std ( 4:0 ) mode ( 2:0 ) cl_rnd ( 2:0 ) v_blank_size_odd(7:0) v_blank_size_even ( 7:0 ) f_offset_odd ( 7:0 ) f_offeset_even ( 7:0 ) noise_red ( 7:0 ) ff_mode ( 1:0 ) v_offset_odd ( 7:0 ) v_offeset_even ( 7:0 ) cc_blank_start_line(7:0) cc_blank_end_line ( 7:0 ) sobel_threshold ( 3:0 ) tvsf ( 7:0 ) thsf ( 7:0 ) md_mode ( 1:0 ) md_threshold tv32 ( 7:0 ) diff3t ( 15:0 ) active_line_field ( 10:0 ) active_pixel_line ( 10:0 ) msf ( 18:16 ) msf ( 15:0 ) crop_h_line_size ( 11:0 ) crop_v_frame_size ( 11:0 ) crop_v_crop_size ( 11:0 ) m32 ( 15:0 ) sequence ( 3:0 ) detail_enh ( 9:0 ) crop_h_crop_size ( 11:0 ) add_lines_bottom_f1 add_lines_bottom_f2 v_blank1_lastline ( 11:0 ) f_vbi2_offset ( 3:0 ) m32 ( 18:16 ) id_mode(1:0) diff3t ( 18:16 ) no_line_delays ( 9:0 ) fdc_mode ( 1:0 ) input_h_blank_words_per_line ( 11:0 ) output_h_blank_size ( 11:0 ) add_lines_top_f2 om_mode ( 2:0 ) v_field2_lastline ( 11:0 ) v_field1_lastline ( 11:0 ) v_blank2_lastline ( 11:0 ) f_vbi1_offset ( 3:0 ) output_h_line_size ( 12:0 )
gf9330 data sheet 24 of 42 proprietary and confidential 18283 - 4 june 2004 3.5.3 control register definitions the host interface internal registers are divided into three classes: user configurable (uc), auto-configurable (ac), and read-only (ro). address locations 0 through 14 contain paramete rs which may be configured by the user. locations 15 through 31 are automatically configured based on the std[4:0] and mode[2:0] registers, but can be user configured if desired. address 0 contains three status re gisters lock_32, ff_detect, and sequence[3:0] which can only be read. writing to the read-only registers will have no effect on their contents. table 3-5: control register definitions address bit location register name class description default 0 4:0 std[4:0] uc defines the video standard as described in 3.1 supported input video formats . 00000 7:5 mode[2:0] uc defines the gf9330 operating mode: 000: interlaced to progressive mode 001: field merging mode 010: film rate down conversion mode 011: film rate down conversion (progressive segmented frame) mode 111: bypass mode (video pass through mode) 000 11:8 sequence[3:0] ro provides the detec ted field sequence number from the 3:2 detection circuit. calculated 12 ff_detect ro set to '1' if a video freeze frame has been detected. calculated 13 lock_32 ro set to '1' if a 3:2 vi deo sequence has been detected. calculated
gf9330 data sheet 25 of 42 proprietary and confidential 18283 - 4 june 2004 1 1:0 ff_mode[1:0] uc defines the freeze frame operating mode: 00: manual freeze frame detection/compensation 01: automatic freeze frame det ection/compensation (default value) 10: disabled 11: reserved 01 2 ff_en_bit uc enables (1) or disabl es (0) freeze frame detection / compensation when in manual freeze frame mode, i.e. ff_mode = 00. 01 5:4 md_mode[1:0] uc defines the motion detection and compensation mode: 00: disabled 01: automatic 10: reserved 11: reserved 01 6 mode_32 uc selects the internal 3:2 sequence detection when set to 0, otherwise uses external se quence from the input pins, xseq[3:0]. 0 7 cc_blank_en uc enables blanking in the close captioned video region. 0 10:8 cl_rnd[2:0] uc defines the clipping and rounding output format: 000: 12-bit output with 10.2 (.25 lsb) resolution 001: 10-bit output clipped/rounded from 0 to 1023 010: 10-bit output clipped/rounded from 4-1019 011: 10-bit output y clipped/rounded from 64 to 940, cr/cb clipped/rounded from 64 to 960 100: reserved 101: 8-bit output clipped/rounded from 0 to 255 110: 8-bit output rounded/clipped from 1 to 254 111: 8-bit output y clipped/rounded from 16 to 235, cr/cb clipped/rounded from 16 to 240 000 11 crop_en uc enables output video cropping based on crop_v_crop_size, crop_v_frame_size, crop_h_crop_size and crop_h_line_size parameters. 0 12 fvh_en_bit uc enables the gf9330 to use external fvh control in place of embedded trs. 0 13 f_polarity uc defines the polarity of t he f_in pin. when set to '1', f follows normal convention where f_in is '0' for field 1(odd) and '1' for field 2 (even). 1 14 v_polarity uc defines the polarity of the v_in pin. when set to '1', v_in follows normal convention where v_in is '1' in the vertical blanking region. 1 15 h_polarity uc defines the polarity of the h_in pin. when set to '1', h_in follows normal convention where h is '1' in the horizontal blanking region. 1 table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 26 of 42 proprietary and confidential 18283 - 4 june 2004 27:0 f_offset_even[7:0] uc d efines the number of lines from the f_in pin eav transition to the vertical blanking interval following the even field. this parameter has a maximum value of 255. 00000000 15:8 f_offset_odd[7:0] uc defines the number of lines from the f_in pin eav transition to the vertical blanking interval following the odd field. this parameter has a maximum value of 255. 00000000 37:0 v_offset_even[7:0] uc defines the number of lines from the v_in pin eav transition to the end of the even active vide o field region. this parameter has a maximum value of 255. 00000000 15:8 v_offset_odd[7:0] uc defines the number of lines from the v_in pin eav transition to the end of the odd active video field region. this parameter has a maximum value of 255. 00000000 47:0n oise_red[7:0] uc the upper five bits of this parameter adjust the noise reduction level applied to the video image, the resolution of the adjustment is defined by the lower 3-bits: noise reduction = y / x y = noise_red[7:3] x = noise_red[2:0] 0 <= y <= 31 x = 1 | 2 | 4 a higher value represents more noise reduction with greater resolution. 00100001 15:8 standard configuration registers uc must be set to default value. 01000100 5 15:0 ff_det_hv[15:0] uc freeze frame detection setting. see 3.11.4 static and freeze frame detection/compensation ie32h 6 7:0 cc_blank_end_ line[7:0] uc defines the last line number at which to end closed captioned blanking. for this parameter, line 0 is defined as the first active line of the field/frame. 0000000 15:8 cc_blank_start_ line[7:0] uc defines the first line number at which to start closed captioned blanking. for this parameter, line 0 is defined as the first active line of the field/frame. 00000000 7 4:0 freeze_frame_ threshold[4:0] uc defines the freeze frame detection threshold, a low value causes noise to have a larger impact on freeze frame detection. 10000 (16 decimal) 15:9 tv32[7:0] uc defines the threshold for the detection of vertical motion between two consecutive fields . a higher value will increase the sensitivity. 00101000 (40 decimal) table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 27 of 42 proprietary and confidential 18283 - 4 june 2004 8 5:0 standard configuration registers uc must be set to default value. 100100 15:6 detail_enh[9:0] uc defines the detail enhancement configuration. the upper five bits of this word adjust the high frequency detail in the image. the lower 5-bits control the resolution or granularity. a higher value represents more detail with higher granularity. detail enhancement = y / x y = detail_enh[9:5] x = detail_enh[4:0] 0 <= y <= 31 x = 1 | 2 | 4 | 8 | 16 00000000 01 9 11:0 crop_h_line_size [11:0] uc specifies the length of the line to output, following the cropped pixels on the left side of the line. 00000000 0000 10 11:0 crop_h_crop_size [11:0] uc specifies the number of active pixels to blank at the beginning of each line. 00000000 0000 11 11:0 crop_v_frame_ size[11:0] uc specifies the number of lines to output, following the cropped lines at the top of the frame (or field). 00000000 0000 12 11:0 crop_v_crop_ size[11:0] uc specifies the number of active li nes to blank at the beginning of each frame. 00000000 0000 14,13 2:0, 15:0 standard configuration registers uc must be set to default value. 00080h (128 decimal) 16,15 2:0, 15:0 msf[18:0] uc represents the num ber of pixels per sm allest active field divided by a scaling factor required to estimate same frame detection. a higher value also m eans vertical edges will have more effect on the detection of same frames. the equation is as follows: msf = #active_pixels_per _smallest_field / 2 7 calculated 18, 17 2:0, 15:0 diff3t[18:0] uc represents the number of active pixels per smallest field divided by a factor required to estimate the odd and even pattern detection. the equation is as follows: diff3t = #active_pixels_per_smallest_field /2 7 calculated 19 7:0 v_blank_size_ even[7:0 ] ac defines the number of lines that comprise the vertical blanking interval that follows the even input field. this parameter has a maximum value of 255. auto 15:8 v_blank_size_ odd[7:0] ac defines the number of lines that comprise the vertical blanking interval that follows the odd input field. this parameter has a maximum value of 255. auto 20 10:0 active_line_ field[10:0] ac defines the number of active lines per smallest input field. auto 15:12 v_blank_offset [3:0] ac for 3:2 pull-down compensation, this parameter must provide the difference (if any) in number of input active lines per frame and the number of output active lines per frame. auto table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 28 of 42 proprietary and confidential 18283 - 4 june 2004 21 10:0 active_pixel_ line[10:0] ac defines the number of active pixels per video input line. auto 12 format_sd ac used to configure th e gf9330 sdram controller. set to ?1? when in 24-bit mode. this bit is auto-configured based on standard and mode selection. auto 13 progressive_ input ac when set to ?1?, configures t he gf9330 to accept a progressive video format. this bit is aut o-configured based on standard and mode selection. auto 15:14 id_mode[1:0] ac defines the type of video sequence for input video de- multiplexing. when set to "00" the input represents a 4:2:2 sequence, "01" represents a 4:1:1 sequence, and "10" represents an hd format. this word can be auto-configured based on video standard and mode. auto 22 11:0 input_h_blank_ words_per_line [11:0] ac defines the number of horizontal blanked input words per line which corresponds to 2 times the number of blanking pixels per line for 4:2:2 sd modes and is equal to the number of pixels per line for hd formats. this value can be auto-configured. auto 12 h_blank_size_ 1half ac reserved for output video formats requiring the equivalent of ? pixel line size resolution. this occurs for std 0, mode 2 and 3 only. auto 13 field2_has_top_ line ac set to ?1? when field 2 line one is the first line in the video frame (smpte 260m). auto 14 even_field_one_ more ac set to ?1? for video standards that have an even number of lines per frame (smpte 295m). auto 15 odd_field_one_ more ac set to ?1? for video standards that have an even number of lines per frame (smpte 295m). auto table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 29 of 42 proprietary and confidential 18283 - 4 june 2004 23 9:0 no_line_delays [9:0] ac defines the number of line delays to implement within the external field delay. this value is auto-configured based on standard and mode. the calculation is: no_line_delays = (total number of lines per frame -7) / 2. auto 11:10 fdc_mode[1:0] ac defines the fiel d delay controller mode for output video formatting: 00: i to p mode 01: psf to p 10: 30i to 24p 11: 30i to 24psf auto 12 frame_regen ac defines frame timing rege neration. this occurs for all 30i-24p and 30i-24psf modes. auto 15:13 om_mode[2:0] ac defines the gf9330 video output mode: 000: sd bypass 001: sd i to p or field merging 010: sd i to p 011: sd i to psf 100: hd bypass 101: hd i to p or field merging 110: hd i to p 111: hd i to psf this value can be auto-configured based on standard and mode. auto 24 12:0 output_h_line_ size[11:0] ac represents the total number of pixels (active plus blanking) per output line. auto 25 11:0 output_h_blank _size[11:0] ac defines the number of blanking pi xels per line at the output. auto 15:12 f_vbi2_offset[3:0] ac defines the number of lines to wait before the rising f transition in the vertical blanking interval on the output. auto 26 11:0 v_blank1_lastline [11:0] uc defines the last line of the first blanking interval, where line 1 is the first blank line of the vertical blanking interval that precedes the odd field or first frame. auto 15:12 f_vbi1_offset[3:0] ac defines the number of lines to wait before the falling f transition in the vertical blanking interval on the output. auto 27 11:10 v_field1_lastline [11:0] uc defines the last line of the first active video field. auto 14:12 add_lines_bottom _f2 uc defines the number of lines to add to the bottom of field 2 (not used). auto 28 11:10 v_blank2_lastline [11:0] uc defines the last line of t he second blanking interval. auto 14:12 a dd_lines_bottom _f1 uc defines the number of lines to add to the bottom of field 1 (not used). auto table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 30 of 42 proprietary and confidential 18283 - 4 june 2004 3.6 closed caption blanking the gf9330 provides a blanking func tion for selected input video lines. consecutive lines within each input field are blanked when this function is enabled, beginning with the cc_blank_start_line and ending with the cc_blank_end_line. the blanking is appl ied prior to any processing of the video data. the blanking function is enabled with the cc_blank_en bit. blank_start_line and blank_end_line are each allocated 8-bits within the host interface. 3.7 programmable noise reduction and detail enhancement the gf9330 performs an efficient techni que for high frequency noise reduction and detail enhancement. there are 256 levels of control provided by the noise_red[7:0] bits within the host interface. high frequency details that are detected with a two-dimensional high pass filter are enhanced using a non-linear function mapp ing between input and output signal. there are 512 levels of control provided by the detail_enh[9:0] bits within the host interface. 29 11:0 v_field2_lastline [11:0] uc defines the last line of the second active video field. auto 14:12 a dd_lines_top_f2 ac defines the number of lines to add to the top of field 2 (not used). auto 30 0 ext_memclk_sel ac controls the selection of the sdram clock source. for vclk_in frequency less than 36 mhz, the internal clock doubler can be used, in all other modes an external source is required (memclk_in). auto 1 voclk_x1_sel ac normally set for hd modes where the output video clock is equal to the input video clock frequency and is set to '0' for sd cases where the output video clock is double the video input clock frequency. auto 2 clk_x1_se ac normally set for all hd m odes and is '0' for all other cases. auto 31 0 s tart_operation uc using external f_in, v_in and h_in signals, this parameter must be set following the completion of programming the f_in, v_in and h_in offsets. 0 15 cmd_reset uc forces the gf9330 to enter a reset state. this commanded reset remains in effect until this parameter is cleared with a subsequent command. 0 table 3-5: control register definitions (continued) address bit location register name class description default
gf9330 data sheet 31 of 42 proprietary and confidential 18283 - 4 june 2004 3.8 reset the reset pin will reset all internal logic to it 's default conditions when set low. on power up it is recommended to reset the device to ensure all internal registers are set to their default stat e. when applying a reset, the gf9330 will load in the std[4:0] and mode[2:0] settings from the external pins. if no further configuration is done, these settings will be used for the operatio n of the device. 3.9 modes of operation the gf9330 supports stand-alone, co-processor enabled, pass-through and film rate down conversion modes of operation. table 3-6: modes of operation: mode[2:0] shows the basic operating modes for the gf9330 as selected using the mode[2:0] control bits or through the hos t interface using the mode[2:0] register, address [0][7:5]. 3.9.1 de-interlacing mode (mode=000) when set to operate as a de-interlacer the gf9330 can operate as a ?stand-alone? device performing motion adaptive processi ng. to enable multi-directional edge and vertical motion detection the gf9330 must be connected to the gf9331 as described in 3.3 seamless interface to the gf9331 motion co-processor for directional filter control . segmented frame to progressive frame conver sion is also supported in this mode. this function is performed when the pr ogressive segmented frame input video format is selected on either the external pins or host interface register std[4:0]. 3.9.2 de-interlacing mode with pull-down compensation (mode=001) when set to operate in this mode, the gf9330 can operate as a ?stand-alone? device performing motion adaptive processing with added 3:2 pull-down compensation. to enable multi-directional edge and vertical motion detection the gf9330 must be connected to the gf9331 as described in 3.3 seamless interface to the gf9331 motion co-processor for directional filter control . table 3-6: modes of operation: mode[2:0] mode description 000 motion adaptive de-interlacing of input video signal. 001 de-interlacing of input video signal with pull-down compensation. 010 film rate down conversion mode (60hz -> 24hz). 011 film rate down conversion mode (60hz -> 24hz segmented frame) 100 to 110 reserved 111 video pass through mode.
gf9330 data sheet 32 of 42 proprietary and confidential 18283 - 4 june 2004 the gf9330 will provide 3:2 sequence comp ensation (field me rging) for film source material. when us ing internal 3:2 sequence detection, th e gf9330 will perform "field-merging" for 3:2 sequences, or will revert to vt processing when no 3:2 sequence is identified. the 3:2 seque nce can be internally detected (host interface bit, mode_32 = 0), or suppli ed via the external sequence pins (xseq[3:0]) for mode_32 = high. with the external sequence selected, the device will revert back to vt processing if the exter nal sequence pins have an invalid code (i.e. a to f) . the xseq[3:0] value should be changed during the sixth blank line of each vertical blanking interval. figure 3-12: sequence detection input signals 3.9.3 film rate down conversion mode (mode= 010) when configured to operate as a film rate down converter, the gf9330 removes 3:2 sequences from the input video stre am and outputs 24hz progressive scan video. no filtering of the signal is perform ed in this mode of operation. the external 3:2 sequence pins (xseq[3:0]) are used in this mode, the sett ing of the mode_32 bit has no effect. note: in this mode, 3:2 compensation remains in effect at all times. 3.9.4 film rate down conversion mo de, segmented frame output (mode= 011) this mode operates in the same manner as the film rate down converter mode, but outputs the progressive scan video in segmented frame format. 3.9.5 video pass thro ugh mode (mode=111) the gf9330, operating in pass-through mode, will pass through only the active portion of the input video si gnal. all other ancillary data will be lost from the input data stream. the video channel is maintained in bypass mode, however, no processing takes place. therefor e, field buffers are still in use and the chip must be in a known programmed state. a b o e original film material (24p) gf9330 video input (30i) o e o e o e o e c d sequence (xseq[3:0]) 1 0 2 3 4 5 6 7 8 9 0
gf9330 data sheet 33 of 42 proprietary and confidential 18283 - 4 june 2004 3.10 output data formats the gf9330 supports multiple output da ta formats. the output data format depends on the input format selected as well as the defined operating mode. table 3-7: output formats specifies the available output formats for the gf9330. table 3-7: output formats std input format de-interlacing film rate down-conversion bypass i-to-p convert mode=000 field merging mode=001 i-to-p convert mode=010 i-to-psf convert mode=011 mode=111 0 525i (30/1.001) smpte 125m 525p (60/1.001) smpte 293m see note: a 525p (60/1.001) smpte 293m see note: a 525p (24/1.001 see note: a 525p (24/1.001) see note: a see note: a 1 reserved na na na na 2 525i (30/1.001) smpte 267m - 16x9 525p (60/1.001) 16x9 see note: a 525p (60/1.001) 16x9 see note: a 525p (24/1.001) 16x9 see note: a 525psf (24/1.001) 16x9 see note: a see note: a 3 reserved 4 625i (25) ebu tech 3267 625p (50) itu-r bt.1358 see note: a 625p (50) itu-r bt.1358 (2:2 pulldown comp.) see note: a 625p (25) (2:2 pulldown comp.) see note: a 625psf (25) (2:2 pulldown comp.) see note: a see note: a 5 reserved 6 625i (25) 16 x9 itu-r bt.601 part b 625p (50) 16 x 9 see note: a 625p (50) 16 x 9 see note: a 625p (25) 16 x 9 see note: a 625psf (25 )16 x 9 see note: a see note: a 7 reserved 8 525p (60/1.001) smpte 293m na na na na see note: a 9 reserved 10 reserved 11 reserved 12 625p (50) itu-r bt-1358 na na na na see note: a 13 625p (50) 16x9 na na na na see note: a 14 generic sd 4:1:1 refer to 3.2.2 generic input format signalling see note: a 15 generic sd 4:2:2 refer to 3.2.2 generic input format signalling see note: a
gf9330 data sheet 34 of 42 proprietary and confidential 18283 - 4 june 2004 16 720p (60 & 60/ 1.001) smpte 296m- 2001 na na na na see note: b 17 720p (30 & 30/ 1.001) smpte 296m- 2001 na na na na see note: b 18 1080p (30 & 30/ 1.001) smpte 274m na na na na see note: b 19 720p (50) smpte 296m- 2001 na na na na see note: b 20 1080p (25) smpte 274m na na na na see note: b 21 720p (25) smpte 296m- 2001 na na na na see note: b 22 1080p (24 & 24/ 1.001) smpte 274m na na na na see note: b 23 720p (24 & 24/ 1.001) smpte 296m- 2001 na na na na see note: b 24 1080i (30 & 30/ 1.001) smpte 274m 1080p (60 & 60/ 1.001) smpte 274m (system #1 and #2) see note: c 1080p (60 & 60/ 1.001) smpte 274m (system #1 and #2) see note: c 1080p (24 & 24/1.001) smpte 274m see note: b 1080psf (24 & 24/ 1.001) draft rp may 99 see note: b see note: b 25 1080psf (30 & 30/1.001) smpte rp211- 2000 1080p (30 & 30/ 1.001) smpte 274m see note: d na na na see note: b table 3-7: output formats (continued) std input format de-interlacing film rate down-conversion bypass i-to-p convert mode=000 field merging mode=001 i-to-p convert mode=010 i-to-psf convert mode=011 mode=111
gf9330 data sheet 35 of 42 proprietary and confidential 18283 - 4 june 2004 26 1080i (25) smpte 274m 1080p (50) smpte 274m (system #3) see note: c 1080p (50) smpte 274m (system #3) (2:2 pulldown comp.) see note: c 1080p (25) smpte 274m (system #9) (2:2 pulldown comp.) see note: b na see note: b 27 1080psf (25) smpte rp211- 2000 1080p (25) smpte 274m (system #9) (psf to p) see note: d na na na see note: b 28 1080i (25) smpte 295m 1080p (50) smpte 295m (system #1) see note: c 1080p (50) smpte 295m (system #1) (2:2 pulldown comp.) see note: c 1080p (25) smpte 274m (system #9) (2:2 pulldown comp.) see note: b na see note: b 29 1080psf (24 & 24/1.001) smpte rp211- 2000 1080p (24 & 24/ 1.001) smpte 274m (system #10 & #11) (psf to p) see note: d na na na see note: b 30 1035i (30 & 30/ 1.001) smpte 260m 1035p (60&60/ 1.001) see note: c 1035p (60&60/ 1.001) see note: c 1035p (24&24/1.001) see note: b 1035p (24&24/1.001) see note: b see note: b 31 generic hd 4:2:2 refer to 3.2.2 generic input format signalling see note: b a.y/c output multiplexed on y1_out[11:0]. b. y output on y1_out[11:0] c output on c1_out[11:0]. c.odd (first) pixel y data on y1_out[11:0], even (second) pixel y data on y2_out[11:0], odd (first) pixel c data on c1_out[11:0 ], even (second) pixel c data on c2_out[11:0]. d.these standards cannot be used in stand alone mode. om_mode[2:0] r egister within the host interface must be configured to ?11 0? in order to achieve output port operation as described in b . table 3-7: output formats (continued) std input format de-interlacing film rate down-conversion bypass i-to-p convert mode=000 field merging mode=001 i-to-p convert mode=010 i-to-psf convert mode=011 mode=111
gf9330 data sheet 36 of 42 proprietary and confidential 18283 - 4 june 2004 3.10.1 output video frame cropping the gf9330 provides programmable output video cropping in both the horizontal and vertical directions. any rectangular window within the full output active frame (or field) is selectab le for output, with all video data outside of this rectangular window cropped (set to the blanking leve l). the h_out, v_out, f_out signals are generated to provide timing for the cropped video frame. the embedded trss remain in the original positions. output video cropping is enabled with th e crop_en bit within the host interface. cropping in the horizontal direction is implemented based on the settings of the crop_h_crop_size and crop_h_line _size. the crop_h_crop_size parameter specifies the number of active pi xels to blank at the beginning of each line. the crop_h_line_size parameter spec ifies the length of the line to output, following the cropped pixels on the left side of the line. crop_h_crop_size and crop_h_line_size are each allocated 12-bits within the host interface. cropping in the vertical direction is implemented based on the settings of the crop_v_crop_size and crop_v_fra me_size. the crop_v_crop_size parameter specifies the number of active lines to blank at the beginning of each frame. the crop_v_frame_size parameter specifies the number of lines to output, following the cropped lines at the top of the frame (or field). crop_v_crop_size and crop_v_frame_size are each allocated 12-bits within the host interface. valid h_out, v_out and f_out are always present even when output signals contain embedded trs signals. when outputting one of the standards with embedded trss, h_out, v_out and f_ou t is synchronized with the gf9330?s output data stream (v_out and f_out transition on eav sequences). refer to figure 3-13: output video cropping for a pictorial representation of the cropping function. figure 3-13: output video cropping available output video frame crop_v_crop_size cropped video frame crop_v_frame_size crop_h_crop_size crop_h_line_size horizontal blanking region vertical blanking region h_out v_out
gf9330 data sheet 37 of 42 proprietary and confidential 18283 - 4 june 2004 3.10.2 12-bits output resolution all output data busses are 12-bits in tota l resolution. output y data is always an unsigned data format. output cr cb is a lways in a offset bi nary data format. relative to the input data stream the 12 -bits outputs are form atted as 10.2 (2 lsb extensions). 3.10.3 controllable rounding and clipping on output data the gf9330 provides a wide range of round/clipping options based on the setting of cl_rnd[2:0] bits within th e host interface as shown in table 3-8: cl_rnd[2:0] . 3.11 sequence detection the gf9330 supports two modes of operating with respect to 3:2 sequence detection (internal and external modes) as described in table 3-9: 3:2 mode select . one bit in the host interface is reserved for the mode_32 bit. table 3-8: cl_rnd[2:0] cl_rnd[2] cl_rnd[1] cl_rnd[0] description 0 0 0 12-bit output. all channels rounded to 10.2 output resolution. 0 0 1 10-bit output #1. data clipped/rounded to 0 to 1023. 0 1 0 10-bit output #2. data clipped/rounded to 4 to 1019. 0 1 1 10-bit output #3. y data clipped/rounded 64 to 940. cr/cb clipped/rounded 64 to 960. 100reserved 1 0 1 8-bit output #1. data clipped/rounded to 0 to 255. 1 1 0 8-bit output #2. data clipped/rounded to 1 to 254. 1 1 1 8-bit output #3. y data clipped/rounded 16 to 235. cr/cb clipped/rounded 16 to 240.
gf9330 data sheet 38 of 42 proprietary and confidential 18283 - 4 june 2004 3.11.1 internal 3:2 detection when set to operate in internal 3:2 detect mode, the gf9330 can automatically detect a 3:2 pull-down sequence in the incoming video data stream. if a 3:2 sequence is detected, the gf9330 sets the lock_32 control bit in the host interface to ?1?. the lock_32 pin is al so asserted high once the sequence has been detected. the actual 3:2 sequence information is reported in the sequence[3:0] register within the host interface and on the xseq[3:0] pins. refer to figure 3-12: sequence detection input signals for a pictorial representation of the 3:2 sequence reporting. 3.11.2 external 3:2 detection when set to operate in external mode, the user will supply the 3:2 sequence information to the xseq[3:0] pins. the gf9330 uses this information to properly de- interlace the input signal or to perform 60hz to 24hz conversion depending on the state of the mode[2:0] register in the host interface or mode[2:0] pins. when operating in this mode the input 3:2 sequence information relates to the input data stream. the 3:2 sequence information requires updating during the first blank line of the vertical blanking interval, identifying the sequence number for the following field. 3.11.3 sequence detect ion and compensation the gf9330 supports external 2:2 se quence detection. a lock_22 pin is provided to indicate the presence of a 2: 2 sequence. the sequence information is inherently embedded in the interlaced video input data, and is identified with the f_in signal (either derived from the embed ded trss or supplied from the external pin). the lock_22 signal will be updated during the first line of each vertical blanking interval. table 3-9: 3:2 mode select mode_32 description 0 internal. the 3:2 sequence is automatically detec ted in the input data stream. the gf9330 reports 3:2 lock and 3:2 sequence information in the host interface registers called lock_32 and sequence[3:0]. the gf9330 also reports this information on the xseq[3:0] pins when configured as outputs. 1 external. the gf9330 accepts a 3:2 sequence from the xseq[3:0] pins configured as inputs.
gf9330 data sheet 39 of 42 proprietary and confidential 18283 - 4 june 2004 3.11.4 static and fr eeze frame detect ion/compensation the gf9330 operates in either disabled, automatic or manual mode for detection and compensation of freeze frame condit ions within the video input stream. when set to operate in disabled mode (host interface bits, ff_mode=10), the gf9330 disables the internal freeze frame detection and compensation circuitry and also ignores any information presented to the ff_en pin or the host interface bit, ff_en_bit. when set to operate in automatic mode (ff_mode[2:0]=01) the gf9330 internally detects and compensate s for freeze frame situations. when a freeze frame situation is detected, t he gf9330 reports this in the ff_detect status bit found in the host interface. this bit is updated at the beginning of a field and remains valid for the remainder of the field. when set to operate in manual mode (ff_mode=00) the gf9330 monitors the ff_en pin and the host interface bit, ff_en_bit to enable or disable freeze frame compensation. static and freeze frame detection compensation is further described in table 3-10: ff_mode[1:0] . in order to manually force the freeze frame detector in the gf9330 into freeze in static or freeze in motion, the following parameters must be set as follows: 1. freeze in static: uses the temporal filter only. msf = 7fffh ff_det_hv = 0000h ff_en_bit = 1 2. freeze in motion: uses both the vertical and temporal filter. msf = 0000h ff_det_hv = ffffh ff_en_bit = 0 note: when using the freeze in motion settings when th e image is static, there will be vertical ringing along the horizontal edges. 3.11.5 motion detection and compensation the gf9330 operates in disabled or automatic mode for motion detection and compensation. when set to operate in disable mode (host interface bits, table 3-10: ff_mode[1:0] host interface ff_mode[1:0] register external ff_en pin host interface ff_en_bit description 00 0 0 manual: freeze frame detec tion and compensation disabled 0 1 manual: perform freeze frame compensation 10 11 01 x x automatic freeze frame detection/compensation 10 x x freeze frame detection and compensation disabled 11 x x reserved
gf9330 data sheet 40 of 42 proprietary and confidential 18283 - 4 june 2004 md_mode=00), the gf9330 does not perf orm internal motion detection and compensation. when set to operate automatic mode (md_mode=01) the gf9330 internally detects and compensates for motion. motion detection and compensation control is further described in table 3-11: md_mode[1:0] . 3.11.6 processing latency in de-interlacing mode (with the exception of progressive segmented frame to progressive format conversion), the gf 9330 processing latency is constant regardless of input or output format sele ction. in all other modes, (including progressive segmented frame to progress ive format conversion and film rate down conversion) the gf9330 processi ng latency is unique yet constant regardless of input or output format selection. for standard de-int erlacing the delay will be 1 fi eld 6 lines and 91 pixels. for 3:2 detection and compensation to both 24p a nd 24psf the delay will be 1 frame 4 lines and 8 pixels. in bypass mode the delay is always 569 lines. table 3-11: md_mode[1:0] host interface md_mode[1:0] register description 00 disabled mode 01 automatic mode 10 reserved 11 reserved
gf9330 data sheet 41 of 42 proprietary and confidential 18283 - 4 june 2004 4. package dimensions figure 4-1: package dimensions 1 2 3 4 5 6 7 8 91011121314151617181920 y w v u t r p n m l k j h g f e d c b a 24.00 ref. 4.00, 45? (4x) 24.00 ref. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 y w v u t r p n m l k j h g f e d c b a pin #1 27.00 ?0.20 24.13 1.27 27.00 ?0.20 24.13 1.27 1.00 (3x) ref. 0.75 ?0.15 (x328) 0.60 ?0.10 2.33 ?0.13 1.17 ref. 0.56 ref.
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification data sheet the product is in a development phase and specifications are subject to change without notice. gennum reserves the right to remove the product at any time. listing the product does not constitute an offer for sale. gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. ? copyright june 2001 gennum corporation. all rights reserved. printed in canada www.gennum.com gf9330 data sheet 42 of 42 proprietary and confidential 18283 - 4 june 2004 42 revision history version ecr date changes and / or modifications 4 133231 june 2004 correction to text for bypass mode and memories used. changed document template. 3 october 2002 update to document information and figures.

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